Article Index |
---|
Front panel interface controllers using CPLDs and Verilog |
Hex To 7-Segment Decoder |
Testbench |
All Pages |
Hex to 7-Segment Display Decoder
Our digit memory is stored as 4-bit hexadecimal values, thus to output to the 7-segment display we require a decoder. The decoder is entirely combinational and doesn't require any latches.It converts our 4-bit value into a 7-bit value representing the activated segments of the display.
module hex_to_7segment(
in,
out
);
input [3:0] in; // our system clock
output [6:0] out;
// the names of each segment and its bit output
parameter A = 7'b0000001;
parameter B = 7'b0000010;
parameter C = 7'b0000100;
parameter D = 7'b0001000;
parameter E = 7'b0010000;
parameter F = 7'b0100000;
parameter G = 7'b1000000;
// combine segment to output the digit (it'so easy!)
assign out =
(in == 4'h0) ? A|B|C|D|E|F :
(in == 4'h1) ? B|C :
(in == 4'h2) ? A|B|G|E|D :
(in == 4'h3) ? A|B|C|D|G :
(in == 4'h4) ? F|B|G|C :
(in == 4'h5) ? A|F|G|C|D :
(in == 4'h6) ? A|F|G|C|D|E :
(in == 4'h7) ? A|B|C :
(in == 4'h8) ? A|B|C|D|E|F|G :
(in == 4'h9) ? A|B|C|D|F|G :
(in == 4'ha) ? A|F|B|G|E|C :
(in == 4'hb) ? F|G|C|D|E :
(in == 4'hc) ? G|E|D :
(in == 4'hd) ? B|C|G|E|D :
(in == 4'he) ? A|F|G|E|D :
(in == 4'hf) ? A|F|G|E :
4'bz;
endmodule