There are four cycles in our previous CPU design, Fetch, Decode, Execute and Store (aka 'Write back'). In our current cpu design these 4 cycles are performed one at a time, thus our CPU executes an instruction from memory for every 4 cycles of the CPU clock. With a few changes we can increase our performance substantially to almost achieve a single instruction per clock cycle.
I figured out a way (after hearing some rumors it was possible) to through plate vias and thru holes using a liquid from a "car defroster repair kit" sold by permatex.com. I found it at Advanced Auto Parts for the cost of about 10$ US. You can also use "Silver Print" made by MG Chemicals (see update below).
My pcb had 10 mil traces and via holes using a #72 drill. Many of the vias worked. Normal through holes like 2.54mm headers also worked, even some large holes worked. Typically the through holes were the best as they were big enough to clear the liquid through without getting clogged. However, with the vacuum table, it should suck the #72 vias fine.
An example of a front panel interface for a digital audio recorder using a Xilinx XC9572XL CPLD interfaced with an Atmel AVR32AP7001 with the NGW100 Eval Kit. The CPLD provides "time multiplexed" sequencing for a 6 digit 7-segment LED display, 8 status LEDs, and detects input from 7 key switches generating a CPU interrupt on a key press or release. The CPLD interfaces with the AVR32AP using a simple 4-bit multiplexed bus. This provides a good example of designing a front panel interface that relieves the duty from the host CPU -- no polling!
Preliminary schematics and PCB artwork are completed for an 400K gate FPGA board capable of running Linux. Features inclu de 8Mb Flash, 32MB SRAM, sound codec, SD Slot and USB. I have completed the schematics and PCB routing but I have not yet tested the design beyond some spice modeling.
I have designed for a few projects I am planning and will also be part of the Your First CPU project for implementing and testing the custom soft processor core and ucLinux.
What good is a cpu without an assembler? In this chapter we use flex and bison (i.e. lex and yacc) to make an assembler for our cpu. The assembler generates a binary file that can be loaded by the verilog $readmemh statement, or in a synthesized FPGA we would use the binary file to initialize the instruction memory inside the FPGAs internal memory blocks.
Before we move on to updating our basic cpu verilog code let us talk a little more about the four basic units of a cpu. These parts are typically called the Datapath, Function Unit or ALU, Memory/Register File and the Control Unit. Any cpu must at least have these four basic blocks.
In this first chapter we learn the very basics of a CPU's core logic. We include basic Function Unit logic such as logical operators and math functions. To keep our first chapter simple, branching is not yet implemented so our programs are strictly linear and cannot include loop constructs. Also, the program code is included directly in the CPU source file.