Yogi rides the new 6 wheeled robotic base platform. Designed in Solidworks and milled on my CNC machine.

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Hacking the XBOX
The original XBOX is a great platform for hacking. In fact, there is a large underground community of Xbox hackers on the Internet.  
FPGA ucLinux Board
Preliminary schematics and PCB artwork are completed for an 400K gate FPGA board capable of running Linux. Features inclu de 8Mb Flash, 32MB SRAM, sound codec, SD Slot and USB. I have completed the schematics and PCB routing but I have not yet tested the design beyond some spice modeling.
Your First CPU!
Follow along with me as I design a very simple CPU using verilog HDL and an FPGA!  
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Tuesday April 16 , 2024
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Mobile Robotic Platform

My new 6-wheeled robot platform provides a good starting point to mount an array of sensors. Though I also plan to use this base to experiment with autonomous robotic behavior, my first plan is to add a web-cam and wireless network and be able to control the robot with my iphone! The goal with the iphone is to develop as natural as possible user interface and one very unlike traditional control interfaces.

I like the idea of controlling a mobile robot with an iphone by using the iphone's accelerometers and digital compass rather than a traditional interface using buttons. The accelerometers add a more natural control interface where movement of the robot and the panning camera is controlled by moving the iphone by changing yaw, pitch and roll. The iphone, and similar emerging devices, are changing the way we interact with the traditionally flat digital realm and instead augmenting reality --- yes, wiki Augmented Reality!

 

 

FPGA ucLinux Board

Preliminary schematics and PCB artwork are completed for an 400K gate FPGA board capable of running Linux. Features inclu de 8Mb Flash, 32MB SRAM, sound codec, SD Slot and USB. I have completed the schematics and PCB routing but I have not yet tested the design beyond some spice modeling.

I have designed for a few projects I am planning and will also be part of the Your First CPU project for implementing and testing the custom soft processor core and ucLinux.

 

Your First CPU - Chapter 4 - Pipelining

There are four cycles in our previous CPU design, Fetch, Decode, Execute and Store (aka 'Write back'). In our current cpu design these 4 cycles are performed one at a time, thus our CPU executes an instruction from memory for every 4 cycles of the CPU clock. With a few changes we can increase our performance substantially to almost achieve a single instruction per clock cycle.

 

PCB Through-hole at Home

I figured out a way (after hearing some rumors it was possible) to through plate vias and thru holes using a liquid from a "car defroster repair kit" sold by permatex.com. I found it at Advanced Auto Parts for the cost of about 10$ US. You can also use "Silver Print" made by MG Chemicals (see update below).

My pcb had 10 mil traces and via holes using a #72 drill. Many of the vias worked. Normal through holes like 2.54mm headers also worked, even some large holes worked. Typically the through holes were the best as they were big enough to clear the liquid through without getting clogged. However, with the vacuum table, it should suck the #72 vias fine.

   

CNC Milling Machine

My CNC Mill is finally completed after about 9 months of obsessive effort. I have already milled a few parts for a second CNC machine, a plastic doggy bone and a few PCBs have been drilled and routed. The plastic doggy bone was only 1 x 1/3 inches but the detail was fantastic!

The accuracy exceeds the measurability of my digital caliper (1/2mil resolution) so I am quite impressed with the results! So far, I am limiting my materials to plastic, machinable wax and Butterboard(tm) but will cut some aluminum shortly.

I have included some details on the construction with a few pictures.

 

Front panel interface controllers using CPLDs and Verilog

An example of a front panel interface for a digital audio recorder using a Xilinx XC9572XL CPLD interfaced with an Atmel AVR32AP7001 with the NGW100 Eval Kit. The CPLD provides "time multiplexed" sequencing for a 6 digit 7-segment LED display, 8 status LEDs, and detects input from 7 key switches generating a CPU interrupt on a key press or release.  The CPLD interfaces with the AVR32AP using a simple 4-bit multiplexed bus. This provides a good example of designing a front panel interface that relieves the duty from the host CPU -- no polling!

   

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